1. Field of the Invention
The present invention relates to an apparatus for calculating an absolute difference, and more specifically, to an apparatus for calculating an absolute difference capable of calculating an absolute difference using an adder.
2. Discussion of Related Art
A conventional arithmetic logic unit (ALU) has performed the various arithmetic operations, which include a subtraction operation in addition to an addition operation and various logical operations, which include a logical sum and a logical product, on the basis of an adder. Meanwhile, in the recurrent applications including the multimedia processing, calculation performance is enhanced by adding calculations of an absolute difference to the ALU in addition to the general operations. The calculation of the absolute difference refers to the calculation of a difference between two integers. The absolute difference between two integers A and B is denoted by |A−B|, and there are various methods of processing this calculation in an efficient manner.
FIG. 1 illustrates the configuration of a conventional apparatus for calculating an absolute difference, which implements an absolute difference calculation using two adders and a multiplexer (MUX). As illustrated, in order to calculate an absolute difference between integers A and B, i.e., |A−B|, first, the A−B calculation is performed using a NOT operation and addition, and the resultant value, i.e., the value of a temporary variable “TMP,” is output. Here, when a code bit of TMP is 0, this denotes a positive number, and thus a final result is output by adding 0 to the value of TMP. Further, when the code bit of TMP is 1, this denotes a negative number, and thus a NOT operation is performed on the value of TMP to calculate an absolute value, and then a final result is output by adding 1 to the value of TMP. As can be seen from FIG. 1, the conventional apparatus for calculating an absolute difference uses two adders and one MUX to calculate the absolute difference.
FIG. 2 illustrates a similar example of calculating an absolute value to that of FIG. 1. FIG. 2 illustrates the configuration of an apparatus for calculating an absolute difference implemented through an XOR operation without an MUX. It may be found that two adders are employed as well.
FIG. 3 illustrates another example of calculating an absolute difference. Here, A+(˜B)+1 operation and A+(˜B) operation are simultaneously performed using two adders, and the results of A+(˜B)+1 operation or (˜(A+(˜B))) operation are output depending on the presence of overflow. In this case, the two adders are used in the same manner as the apparatus for calculating an absolute difference illustrated in FIGS. 1 and 2.
However, when the apparatus for calculating an absolute difference is implemented according to the configuration illustrated in FIGS. 1 to 3 for the purpose of calculating an absolute difference, two adders are mounted on the ALU of a processor, and this increases the burden on a logic area.